(1) Technical Field
The present invention relates to multi-profile memory controllers and computing devices, such as solid-state storage devices, that use these multi-profile memory controllers.
(2) Background Art
Multi-profile memory controllers have been traditionally designed to operate with memory stores or modules that comprise of memory devices which use the same memory device characteristics, such as block size. Some of these multi-profile memory controllers are disposed to operate with memory devices that use flash memory cells which utilize relatively large block sizes, such as 128 Kb or greater. Flash memory devices that have a relatively large block size generally provide better sequential memory access performance than flash memory devices that have a relatively small block size. Larger block sizes are commonly employed because flash memory devices that are disposed with larger block sizes tend to exhibit greater memory density than flash memory devices that use smaller block sizes. In addition, these higher density flash memory devices tend to be generally more cost effective than flash memory devices with less memory density.
A multi-profile memory controller that employs flash memory devices that have relatively large block sizes incurs some disadvantages, however, because it suffers from relatively higher read-modify-write cycle latency, higher random memory access latency and lower random IOPS (input/output operations per second). Consequently, there is a need for a multi-profile memory controller that can operate with memory locations, memory devices, or both that are associated with different memory attributes, different attribute qualifiers, or the like, while minimizing or avoiding some or all of the above described disadvantages.